M2F1G64CB88A4N / M2F2G64CB8HA4N
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR3 SDRAM DIMM Preliminary
REV 0.1 17
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AC Timing Specifications for DDR3 SDRAM Devices Used on Module
Minimum Clock Cycle time (DLL off mode)
tCK(avg)min + tJIT(per)min
tCK(avg)max +tJIT(per)max
Absolute clock high pulse width
Absolute clock low pulse width
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across n=11~50 cycles
tERR(npr)min =(1+
0.68In(n))*tJIT(per)min
tERR(npr)max =(1+
0.68In(n))*tJIT(per)max
DQS, to DQ skew, per group, per access
DQ output hold time from DQS,
DQ low-impedance time from CK,
DQ high-impedance time from CK,
Data setup time to DQS, DQS reference to Vih(ac) / Vil(ac) levels
Data hold time to DQS, DQS reference to Vih(ac) / Vil(ac) levels
DQS, differential READ Preamble
DQS, differential READ Postamble
DQS, differential output high time
DQS, differential output low time
DQS, differential WRITE Preamble
DQS, differential WRITE Postamble
DQS, rising dege output access time from rising CK,
DQS, low-impedance time (Reference from RL-1)
DQS, high-impedance time (Reference from RL + BL/2)
DQS, differential input low pulse width
DQS, differential input high pulse width
DQS, rising edge to CK, rising edge
DQS, falling edge setup time to CK, rising edge
DQS, falling edge hold time to CK, rising edge
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