Elixir M2F2G64CB8HA4N-CG Fiche technique télécharger pdf (Page 15)

M2F1G64CB88A4N / M2F2G64CB8HA4N

1GB: 128M x 64 / 2GB: 256M x 64

Unbuffered DDR3 SDRAM DIMM Preliminary

REV 0.1 15

06/2008

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

DDR3-1066

DDR3-1333

Parameter

Symbol

Min

Max

Min

Max

Units

Command and Address Timing

DLL locking time

tDLLK

512

nCK

Internal READ Command to PRECHARGE Command

delay

tRTP

max(4nCK, 7.5ns)

Delay from start of internal write transaction to internal

read command

tWTR

max(4nCK, 7.5ns)

WRITE recovery time

tWR

Mode Register Set command cycle time

tMRD

nCK

Mode Register Set command update delay

tMOD

max(12nCK, 15ns)

 to  command delay

tCCD

nCK

Auto precharge write recovery + precharge time

tDAL(min)

WR + roundup (tRP/tCK(avg))

nCK

Multi-Purpose Register Recovery Time

tMPRR

ACTIVE to ACTIVE command period for 1KB page size

tRRD

max(4nCK, 7.5ns)

max(4nCK, 6ns)

Four activate window for 1KB page size

tFAW

37.5

Command and Address setup time to CK,  referenced

to Vih(ac) / Vil(ac) levels

tIS(base)

125

Command and Address hold time to CK,  referenced to

Vih(ac) / Vil(ac) levels

tIH(base)

200

140

Calibrating Timing

Power-up and RESET calibration time

tZQinit

512

nCK

Normal operation Full calibration time

tZQoper

256

nCK

Normal operation Short calibration time

tZQCS

nCK

Reset Timing

Exit Reset from CKE HIGH to a valid command

tXPR

max(5nCK,

tRFC(min) +

10ns)

max(5nCK,

tRFC(min) +

10ns)

Self Refresh Timings

Exit Self Refresh to commands not requiring a locked DLL

tXS

max(5nCK,

tRFC(min) +

10ns)

max(5nCK,

tRFC(min) +

10ns)

Exit Self Refresh to commands requiring a locked DLL

tXSDLL

tDLLK(min)

nCK

Minimum CKE low width for Self Refresh entry to exit

timing

tCKESR

tCKE(min) +

1nCK

tCKE(min) +

1nCK

Valid Clock Requirement after Self Refresh Entry (SRE) or

Power-Down Entry (PDE)

tCKSRE

max(5nCK, 10ns)

Valid Clock Requirement after Self Refresh Exit (SRX) or

Power-Down Exit (PDX) or Reset Exit

tCKSRX

max(5nCK, 10ns)

Power Down Timings

Exit Power Down with DLL on to any valid command; Exit

Precharge Power Down with DLL frozen to commands not

requiring a locked DLL

tXP

max(3nCK, 7.5ns)

max(3nCK, 6ns)

Exit Precharge Power Down with DLL frozen to

commands requiring a locked DLL

tXPDLL

max(10nCK, 24ns)

CKE minimum pulse width

tCKE

max(3nCK,

5.625ns)

max(3nCK,

5.625ns)

Command pass disable delay

tCPDED

nCK

Power Down Entry to Exit Timing

tPD

tCKE(min)

9*tREFI

tCKE(min)

9*tREFI

Timing of ACT command to Power Down entry

tACTPDEN

nCK

Timing of PRE or PREA command to Power Down entry

tPRPDEN

nCK

Timing of RD/RDA command to Power Down entry

tRDPDEN

RL+4+1

nCK

Timing of WR command to Power Down entry (BL8OTF,

BL8MRS, BC4OTF)

tWRPDEN

WL+4+(tWR/tCK(a

vg))

WL+4+(tWR/tCK(a

vg))

nCK

Timing of WRA command to Power Down entry

(BL8OTF, BL8MRS, BC4OTF)

tWRAPDEN

WL+4+WR+1

nCK

Timing of WR command to Power Down entry (BC4MRS)

tWRPDEN

WL+2+(tWR/tCK(a

vg))

WL+2+(tWR/tCK(a

vg))

nCK

Timing of WRA command to Power Down entry

(BC4MRS)

tWRAPDEN

WL+2+WR+1

nCK

Timing of REF command to Power down entry

tREFPDEN

nCK

Timing of MRS command to Power Down entry

tMRSPDEN

tMOD(min)

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 21 22

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